Electronic enthusiast network news: This article mainly describes TAKUMI's image IP core reference design can be used for S2C prototype verification platform. S2C announced that TAKUMI, a high-end graphics intellectual property (IP) provider based in Japan, has successfully implemented a series of graphical IP cores, including the GS3000 and GSV3000 IP cores, on the S2C FPGA-based rapid prototyping system. These TAKUMI IP cores have been fully validated in FPGAs and can be easily demonstrated and evaluated by customers, greatly reducing system-on-chip (SoC) integration time.
TAKUMI's GSHARK IP family is a graphical imaging solution that accelerates display rendering on a wide range of embedded systems, including mobile devices, digital home appliances and in-vehicle information systems. Uniquely designed and tailored for embedded systems, the GSHARK-TAKUMI family integrates a wide range of graphical IP cores for optimal configuration for a variety of embedded systems.
S2C CEO Toshio Nakama said: "Integrating a complex IP core, such as 3D graphics image IP, often requires huge verification work in the SoC, such as verifying the correctness of all hardware functions, evaluating SoC bus efficiency and testing software compatibility. And the best way to perform these tasks today is to get the entire design at or near the actual operating speed by using FPGA-based prototyping to debug verification before the actual silicon is available. We are happy to work with TAKUMI. Providing SoC developers with a range of advanced graphics IP cores that have been mapped to FPGA-based prototypes can significantly reduce the time it takes to integrate IP into SoCs and begin software development and testing early."
"Currently, graphics IP is very complex and requires a lot of test patterns to perform complete hardware verification and software testing. Therefore, a reliable, flexible and high-performance FPGA platform is essential." Executive Director, Research and Development, TAKUMI Hiroyuki Nitta said, “We have chosen S2C as our preferred FPGA platform partner because their products are known for their reliability, flexible connection to various SoC interfaces, and a wide range of scalable gate count designs.†TAKUMI Graphical IP The core has been prototyped and can be used as a reference design on the S2C Virtex-6 760 TAI Logic Modules or easily ported to the new Virtex-7 2000T TAI Logic Module series or the Altera StraTIx-4 820 TAI Logic Module series. S2C's complete portfolio of fast FPGA-based prototyping solutions is designed to make prototyping an easy experience, with from 1 to 9 FPGA devices on a single board, from two million up to 180 million ASIC gates Designed in the middle. In addition, S2C offers a complete solution including prototyping and debugging software; DPI, SCE-MI and C-API collaborative modeling; and a large Prototype Ready IP&Attachment library.
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