Semiconductor Manufacturing: Follow or Surpass Moore's Law

Halfway through 2011, choosing to talk about semiconductor process technology at this time is a good time. In the following autumn and winter, the semiconductor industry will face a complete leap forward in process technology. According to the latest news, Intel's 22nm and STMicroelectronics, Taiwan Semiconductor Manufacturing (TSMC) 28nm process should be mass production in the remaining months of this year, while Samsung, UMC and GF (Global Foundries) 28nm should not be later than the second quarter of next year.

It is both coincidental and inevitable that IDM (Independent Design and Manufacturing Corporation) and Foundry (OEM) are intensively updating processes. According to Intel's Tick-Tock (process year-frame year) development model, single-year update process, 22nm is its next process node. For other wafer fabs that choose the 28nm chip, the 28nm process did not achieve the standard yield until this year because of the increasing difficulty of technological development. Many fabs dared to publicly announce mass production.

As this semiconductor manufacturing process is about to be replaced, we may look at the design, manufacturing and foundry from different perspectives to meet the new strategy of semiconductor companies to cope with strategies.

New Process New Advantages The new process has always been the benchmark for the development of the semiconductor industry, and bringing new competitiveness to the product is the biggest driving force for companies to devote their energies to new technologies. The improvement in performance and power consumption of semiconductor products brought about by each generation of process improvement is obvious. High performance, low power consumption, and even smaller dimensions are the three major trends in semiconductor technology. With portable electronic products becoming the mainstream in the market, almost all integrated circuits have become smaller in size. On the same size silicon, the new process allows manufacturers to add more features, increase the speed of the chip, or reduce the functional cost. The main benefit of using 28nm advanced technology is to meet the market demand of customers for high performance, low power consumption, and miniaturization.

As the only general-purpose chip IDM other than Intel that insists on process R&D, Jean-Marc Chery, Senior Vice President and Chief Technology Officer of STMicroelectronics, talks about process improvement and stated that in the consumer electronics market, STB chips (decoders), gateways and 3D (HD) TV is the beneficiary of the process upgrade from the 40 nm technology node to the 32/28 nm node. These new processes can increase the processing performance of the chip by about 30% without any increase in power consumption. In addition, the smaller feature size allows manufacturers to integrate more processing units on each chip to improve computing power and processing performance, for example, to give users an excellent HD 3D TV experience. In terms of network system chips, consumers will get products with data rates of 14-25G bit/s, and the data transmission rate is much higher than the 10-14G bit/s of the previous-generation technology nodes.

Regarding the advantages brought by the new process, Chen Jiaxiang, general manager of TSMC China, introduced that the 28HP process was the first to adopt advanced high dielectric layer/metal gate (HKMG) technology, which was faster than the 40nm process on the same current leakage basis. It is about 25% faster, and the leakage can be reduced by about 50% on the basis of the same speed. The current 28nm process is divided into Gate-First (gate first) and Gate-Last (gate last) two ways. Since Gate-Last technology has the best advantage of both P-type and N-type transistor threshold voltage (Vt) adjustments, TSMC has announced the use of Gate-Last technology for customers in high-performance and low-power processes. On the other hand, TSMC’s leading position in the industry is based on the differentiated competitive advantage of “triple technology, superior manufacturing, and customer partnership”. In 2010, TSMC has provided its customers with 28nm programmable logic gate arrays (FPGAs) with advanced Through Silicon Via and Silicon Interposer chip prototyping services. With its own TSVs and wafer-level packaging technology compatible with integrated circuit manufacturing service providers, TSMC is committed to working closely with customers to develop cost-effective 3D integrated circuit system integration solutions.

Xilinx's new FPGA is a new 28nm product based on TSV technology. Zhang Yuqing, director of sales and marketing of the company's Asia Pacific region, frankly benefits from 28nm process technology. Xilinx has introduced a unified architecture that reduces overall power consumption by half and has the highest level in the industry. The 7-series FPGAs with capacity (2 million logic cells) can not only achieve excellent productivity, but also solve the problems of high cost, complexity, and inflexibility of other methods such as ASIC and ASSP, enabling the FPGA platform to meet increasingly diverse designs. The needs of the community. At the 28 nm process node, static power consumption is an important part of the total power consumption of the device, and sometimes even a decisive factor. Since the key to improving the performance and functionality of available systems is to control power consumption, in order to achieve maximum efficiency, the appropriate process technology must first be selected. Xilinx selected HKMG's high-performance, low-power process technology to enable next-generation FPGAs to minimize static power consumption and ensure the best performance and functional benefits from 28 nm technology. Compared with standard high-performance process technology, high-performance and low-power process technology reduces FPGA static power consumption by 50% and total power consumption by 50%. At the same time, next-generation development tools can reduce dynamic power consumption by 20% through innovative clock management techniques. In addition, through the enhancement of partial reconfiguration techniques, designers can further reduce power consumption and reduce system cost by 33%.

Kevin Kranen, director of strategic alliances at Synopsys, believes there are three main reasons why companies are migrating to advanced processes.

Cost/Wafer Area/Integrity: The goal is to minimize the cost of materials (BOM) for end products such as smartphones, tablets, and smart TVs. GF expects their 28SLP process density to be twice that of the traditional 40LP process. By integrating application processors, graphics, memory controllers, video encoding/decoding, standard connection interfaces (USB, MIPI), and standard wireless interfaces (WiFi, Bluetooth, and LTE) on a single system-on-chip, companies can dramatically reduce End product costs, and can produce smaller and thinner products. One example of the benefits of reduced cost/reduced size after integration is the Apple A5 used on the iPad 2. With the current application at 45nm, integration has made Apple products with significant advantages in cost, performance, and form factor compared to discrete chips.

Power consumption: The many benefits of integration and the use of higher-order nodes help reduce power consumption and extend battery life. GF estimates that compared to the traditional 40G process, the power consumption of each switch in their 28HPP process is reduced by half and the standby power is only 30% at the specified speed.

Performance: Designers can also improve performance from the design section with the same effective power. Compared to the 40LP process, the GF's 28SLP speed is increased by 80%.

New Processes and New Challenges As new processes bring new competitive advantages, they also bring many design and manufacturing challenges to the entire industry. For this reason, designers are required to maintain a good relationship with EDA (electronic design automation) and fabs. Collaborate to meet new design and manufacturing challenges. As the semiconductor industry follows the rules of Moore's Law and strives to multiply the number of transistors integrated on the chip, new technological challenges are constantly emerging. On the premise of not sacrificing power consumption or even reducing power consumption, improving processing performance is another technical challenge urgently needed to be solved by semiconductor manufacturers. This requires the collaboration of the entire industrial chain.

As chip feature sizes shrink, parasitics and device variability increase due to the dispersion of processes below 20nm. Understanding these new effects and how to effectively model them is a big challenge for chip design. According to Jean-Marc Chery, STMicroelectronics works closely with all major EDA companies to provide customers with design tools that help them overcome the design complexity issues associated with new technology nodes. In fact, dealing with the increase in design complexity, providing customers with effective design tools, and ensuring or even shortening time-to-market for customers based on new technology nodes is one of the biggest challenges that semiconductor companies have to address. In fact, for sub-30nm processes, the number of major chip manufacturers that can overcome these challenges is decreasing. Of course, STMicroelectronics is one of these few major manufacturers.

The new process is inseparable from the excellent EDA tools. Tool developers face three high-level challenges in the high-end process stage. There are also several related specific problems and solutions. Challenges in this regard include: The smaller the geometric volume of managing increasingly complex system-on-chip (SoC) chips, the more system-level chip content means more complexity and complexity; Improve system-level architecture verification and implementation, and use pre-verification more. , Easy-to-integrate commercial IP (intellectual property) and the adoption of better and more efficient verification methods; Improve the accuracy of implementation, signoff and verification, and improve throughput/market time/risk.

Talking about the transformation of tools and methods that SoC (system-on-a-chip) designers will encounter in new nodes, Kevin Kranen believes that the new nodes face different challenges: 32nm and 28nm EDA tools have the same requirements. The main challenges faced include the following aspects.

1. Since SiON gate dielectrics are too thin to control, there are challenges in reducing gate leakage and threshold variability. Currently, major chip foundries have turned to new materials and high-k metal gate (HKMG) process technologies (first gate and back gate processes). This change has led to the need to include new design rules in the routing tools and design rule check (DRC) tools.

2. The challenge of operating at the basic limit of 193nm lithography. Designers must step up lithography checks on implementation and signoffs. Currently, leading chip foundries require users to perform some form of lithography inspection before submitting their designs. For example, for different Foundry features, Synopsys offers different tools to help identify and eliminate designs that cause lithography problems and other effects on yield.

3. New process topology modeling challenges for parameter extraction. Currently, leading chip foundries are creating new "via and contact" topologies to improve chip manufacturability and maintain their density. Extraction tools such as STAR RC have been updated to better understand the new via etch effects and intaglio contact technologies.

4. The variability of management parameters, especially the challenges of variability during sign-off. In terms of parameter variability, compared to the situation in the previous process node, the percentage has increased significantly relative to the benchmark data, but the use of worst-case analysis is too pessimistic. At present, chip foundries and designers are beginning to require advanced AOC design and analysis methods to limit variability and provide on-time signoffs. At the same time, EDA tools must have AOCV analysis capabilities.

Correspondingly, there are different requirements for 22/20nm. The main challenges for EDA tools include the following four points.

1. The addition of new restrictive design rules to ensure the use of 193 nm can successfully achieve absolute resolution limit lithography. In order to meet the requirements of these new rules, the layout and routing tools and DRC inspections must be upgraded.

2. Challenges in exceeding the limit of 193nm lithography for some levels. Some chip layers, including vias and metal pitch, cannot be projected in a single mask. This is because these chip layers are too small and too dense in the 20/22nm process and must be patterned in double patterns. The characteristics of a single chip layer are separated in two masks. The double-pattern pattern presents new spacing requirements that may increase the area of ​​the design. However, intelligent placement and routing can ease the effects of the double pattern pattern on the area when it is actually implemented.

3. New extraction requirements - Some 22/20nm processes add new structures and topologies such as indented contacts, requiring new extraction capabilities.

4. Evolution of FINFET/TriGate architectures - Intel that has had a major impact on the entire semiconductor industry announced that they will switch to using 22G chips using TriGate transistors. The FINFET/TriGate architecture has higher requirements for extraction and SPICE simulations, and Synopsys has begun to consider these issues in EDA tools. At the same time, process and equipment engineers must carry out process or equipment simulations on FINFETs and must also have the ability to move from 2D TCAD to 3D TCAD.

From the perspective of the foundry, Chen Jiaxiang introduced that in order to meet the challenge of new design, TSMC and fabless (fabless semiconductor) customers should cooperate earlier, deeper, and closer together, combining the advantages of both parties in the future in the design and technical challenges. . First of all, foundry and fabless should position the product design earlier. Second, both parties should further strengthen the cooperation of silicon IP and jointly pursue the consistency of design tools such as design for manufacturing (DFM) and design specification (RDR). Further solve problems from the design to the production process to improve product quality. Currently, the TSMC 28nm design eco-environment is in place. The latest custom design tools including Reference Flow 12.0 and Analog/Mixed Signal Reference Flow 2.0 are published. , Strengthen the existing open innovation platform design eco-environment, help customers to develop 28nm products faster and better. In addition, the 28nm product has already entered volume production, and the number of 28nm new product designs planned by customers using TSMC's Open Innovation Platform has exceeded 80.