Original link: Learn verilog for a month, wrote a lot of code on the development board, but always understand the problem is not thorough enough, here we write a few examples to simulate the difference between blocking and non-blocking, we first on the code module LED ( CLK, RSTn, scan, flag , c, , one, two, three, four); input CLK; input RSTn; input scan; output flag, c; output [3:0] one, two, three, four; ************************************************** *********/ reg F1,F2; reg a,b; reg [3:0] one,two,three,four; /*************** ***** Non-blocking assignment between signal passing ************************************* **/ always @ ( posedge CLK or negedge RSTn ) // if( !RSTn ) begin F1 <= 1'b1; F2 <= 1'b1; end else begin F1 <= scan; F2 <= F1; end /* ****************** Blocking assignment between signal passes ************************* ***************/ always @ ( posedge CLK or negedge RSTn ) // if( !RSTn ) begin a = 1'b1; b = 1'b1; e Nd else begin a = scan; b = a; end /****************** data plus non-blocking assignment first judged after counting ********** *******************************/ always @ ( posedge CLK or negedge RSTn ) //one <= if( !RSTn Begin one<=0; end else begin if(one==14) one<=0; else one<=one+1; end/***************data plus Blocking assignment first counts and judges ********************************************** / always @ ( posedge CLK or negedge RSTn ) // two<= if( !RSTn ) begin two<=0; end else begin two<=two+1; if(two==14) two<=0; end / ************** Data plus blocking assignment first judged and counted ****************************** *****************/ always @ ( posedge CLK or negedge RSTn ) //three = if( !RSTn ) begin three=0; end else begin if(three==14 ) three=0; else three=three+1; end/************* data plus blocking assignment first counted and judged ************** *******************************/ always @ ( posedge CLK or negedge RSTn ) //four = if( !RSTn ) begin four=0; end else begin four=four+1; if(four==14) four=0; end /**************** ***********************/ assign flag = F2 & !F1;assign c = b & !a;/********* ******************************/ endmodule 2, I use modesim simulation, the following is my test bench `TImescale 1 ps/ 1 psmodule LED_vlg_tst();//constants // general purpose registersreg eachvec;// test vector input registersreg CLK;reg RSTn;reg scan;// wires wire c;wire flag;wire [3:0] four;wire [3 :0] one;wire [3:0] three;wire [3:0] two;// assign statements (if any) LED i1 (// port map - connecTIon between master ports and signals/registers .CLK(CLK) , .RSTn(RSTn), .c(c), .flag(flag), .four(four), .one(one), .scan(scan), .three(three), .two(two)); /*iniTIal begin // cod e that executing only once // insert code here --> begin // --> end $display("Running testbench"); end always // opTIonal sensitivity list // @(event1 or event2 or .... eventn) Begin // code executes for every event on sensitivity list // insert code here --> begin @eachvec; // --> end end endmodule*/initial beginCLK = 0; forever#10 CLK = ~CLK; endinitial beginscan = 0 ;forever#100 scan = ~scan; endinitial beginRSTn = 0;#1000 RSTn = 1;#1000;#1000;#1000;#1000;#1000;#1000;#1000;#1000;$stop;endendmodule is mainly to initialize a signal of CLK and scan, then initialize the reset, and finally set the simulation Time, so that modesim will not be in the simulation state all the time, consume resources, and can also be easily simulated. Quartus and modesim call each other to debug, you can pay attention to my blog, I will not explain specifically here! 3, modesim waveform diagram Everyone noticed the data changes in the red line frame, you can clearly understand the blocking and non-blocking! Microscopic analysis of blocking and non-blocking 1, on the code, specific observation, a, b, c and F1, F2, flage change module LED (CLK, RSTn, scan, flag, a, b, c, F1, F2,); Input CLK; input RSTn; input scan; output flag, a, b, c; output F1, F2; /************************** *********************************/ reg F1,F2; reg a,b; /***** ************************************************** ****/ always @ ( posedge CLK or negedge RSTn ) // if( !RSTn ) begin F1 <= 1'b1; F2 <= 1'b1; end else begin F1 <= scan; F2 <= F1; end /************************************************* **********/ always @ ( posedge CLK or negedge RSTn ) // if( !RSTn ) begin a = 1'b1; b = 1'b1; end else begin a = scan; b = a ; end /*********************************************** ************/ assign flag = F2 & !F1;assign c = b & !a;/******************** *******************/ endmodule The meaning of the code does not explain 2, test ben Ch code, the same as above, not repeated here  3, the above picture to see the waveform
Heaters refer to equipment used for heating. Heating equipment can be roughly divided into: gas heating equipment, electric heating equipment, boiler heating equipment, and electric wall-hung boiler heating according to different heating media and different heating principles.
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Electric blanket-direct contact conduction; quartz tube heater-heat radiation; heater-warm air convection; air conditioner-warm air convection; electric oil heater-slow air convection; far infrared heater-simulation Far infrared radiation from the sun.
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