The best way to eliminate parasitic oscillations during the startup of the MAX2104 is to set it at an initial frequency at which a large Vtune value is required to make the tuning voltage higher than the clamping voltage value. This application note explains this method in detail.
Overview The following article explains why turning off the frequency doubler will eliminate the parasitic oscillations in the MAX2104.
Parasitic oscillation occurs when the tuning voltage Vtune of the varactor is lower than 3.9V. At this point the load resonant tank Q is very low, and the parasitic loop Q is very high. This path is a typical series resonant circuit including low-loss series inductance and resonance of the internal capacitance of the oscillator unit. The high-Q series resonant tank causes parasitic oscillations with low tuning voltage. The series resistance (20Ω) is often used to reduce the Q value of the parasitic mode series resonant tank.
In normal operation, the diode clamping circuit is used to make Vtune higher than 3.92V (Figure 1). The clamping circuit in the application circuit is used to prevent entering the parasitic oscillation mode.
Figure 1. Typical diode clamping circuit
However, the parasitic mode becomes the main problem in the initial power-up sequence. Experiments show that turning off the LO doubler during power-on can resolve parasitic oscillations. The following analysis will explain why turning off the frequency doubler will eliminate the parasitic oscillation in the MAX2104.
Figure 1 shows the charge pump transistor saturation during worst-case steady-state operation. Vtune is clamped to 3.92V to ensure that the oscillator is out of parasitic oscillation mode.
Analysis For example, suppose that the set-top box is initially programmed to lock at 1458MHz and the LO doubler is turned on. In an ideal situation, the PLL works as shown in Figure 2.
Figure 2. Normal PLL operation
In normal operation, the phase frequency of the crystal and the local oscillator is 625kHz; Vtune is about 10.3V, and the local oscillator oscillates at 729MHz. The frequency doubling circuit doubles it to 1458MHz. The equivalent division ratio is programmed to N = 2332.8. The charge pump collapses to maintain balance, and the charge pump sinks and sinks current as needed.
Figure 3. Parasitic mode oscillation
Oscillating in parasitic mode, the local oscillator oscillates at 1410MHz. The local oscillator frequency multiplier is turned on, and this oscillation frequency is doubled to 2820MHz. This will produce a phase discrimination frequency of 1208kHz. Because the crystal phase frequency is much greater than 625kHz, the charge pump sinks as much current as possible to cause the tuning voltage to decrease. This positive feedback keeps the tuning voltage as low as possible. The lower the tuning voltage, the less likely it is to exit the parasitic resonance mode, because the resonant tank has an on-load Q value at the minimum in the fundamental frequency mode oscillation required.
Figure 4. Fixed LO doubler
Figure 4 shows the PLL operation after the LO doubler is turned off. Now the local oscillator is no longer doubled, and the local oscillator comparison frequency is reduced to 604kHz. Because it is lower than the crystal reference phase frequency of 625kHz, the charge pump draws current to increase the tuning voltage. The tuning voltage rose from 3.8V to 31V. When Vtune increases from 3.8V to 31V, the resonant tank's loaded Q value is greatly improved, and it can resonate in the fundamental frequency mode.
Figure 5. Remedies for parasitic mode
Fig. 5 shows the case of exiting the parasitic mode. Due to positive feedback, Vtune is forced to 30V. The charge pump is in continuous current mode. The resonance circuit reaches the maximum oscillation frequency, about 1160MHz. If the frequency doubler is activated in time at this frequency, the PLL will return to the normal operating mode shown in Figure 1. Conclusion From the above analysis, the following conclusions can be obtained:
The best way to eliminate parasitic mode oscillations during startup is to program the PLL to a frequency where a large Vtune value can be obtained. This will make the tuning voltage higher than the clamping voltage value. When this step is implemented, the Vtune diode clamping circuit will ensure that the tuning voltage is higher than the parasitic mode point where the resonant circuit is easy to enter. Turning off the frequency doubler will eliminate parasitic mode oscillations.
Overview The following article explains why turning off the frequency doubler will eliminate the parasitic oscillations in the MAX2104.
Parasitic oscillation occurs when the tuning voltage Vtune of the varactor is lower than 3.9V. At this point the load resonant tank Q is very low, and the parasitic loop Q is very high. This path is a typical series resonant circuit including low-loss series inductance and resonance of the internal capacitance of the oscillator unit. The high-Q series resonant tank causes parasitic oscillations with low tuning voltage. The series resistance (20Ω) is often used to reduce the Q value of the parasitic mode series resonant tank.
In normal operation, the diode clamping circuit is used to make Vtune higher than 3.92V (Figure 1). The clamping circuit in the application circuit is used to prevent entering the parasitic oscillation mode.
Figure 1. Typical diode clamping circuit
However, the parasitic mode becomes the main problem in the initial power-up sequence. Experiments show that turning off the LO doubler during power-on can resolve parasitic oscillations. The following analysis will explain why turning off the frequency doubler will eliminate the parasitic oscillation in the MAX2104.
Figure 1 shows the charge pump transistor saturation during worst-case steady-state operation. Vtune is clamped to 3.92V to ensure that the oscillator is out of parasitic oscillation mode.
Analysis For example, suppose that the set-top box is initially programmed to lock at 1458MHz and the LO doubler is turned on. In an ideal situation, the PLL works as shown in Figure 2.
Figure 2. Normal PLL operation
In normal operation, the phase frequency of the crystal and the local oscillator is 625kHz; Vtune is about 10.3V, and the local oscillator oscillates at 729MHz. The frequency doubling circuit doubles it to 1458MHz. The equivalent division ratio is programmed to N = 2332.8. The charge pump collapses to maintain balance, and the charge pump sinks and sinks current as needed.
Figure 3. Parasitic mode oscillation
Oscillating in parasitic mode, the local oscillator oscillates at 1410MHz. The local oscillator frequency multiplier is turned on, and this oscillation frequency is doubled to 2820MHz. This will produce a phase discrimination frequency of 1208kHz. Because the crystal phase frequency is much greater than 625kHz, the charge pump sinks as much current as possible to cause the tuning voltage to decrease. This positive feedback keeps the tuning voltage as low as possible. The lower the tuning voltage, the less likely it is to exit the parasitic resonance mode, because the resonant tank has an on-load Q value at the minimum in the fundamental frequency mode oscillation required.
Figure 4. Fixed LO doubler
Figure 4 shows the PLL operation after the LO doubler is turned off. Now the local oscillator is no longer doubled, and the local oscillator comparison frequency is reduced to 604kHz. Because it is lower than the crystal reference phase frequency of 625kHz, the charge pump draws current to increase the tuning voltage. The tuning voltage rose from 3.8V to 31V. When Vtune increases from 3.8V to 31V, the resonant tank's loaded Q value is greatly improved, and it can resonate in the fundamental frequency mode.
Figure 5. Remedies for parasitic mode
Fig. 5 shows the case of exiting the parasitic mode. Due to positive feedback, Vtune is forced to 30V. The charge pump is in continuous current mode. The resonance circuit reaches the maximum oscillation frequency, about 1160MHz. If the frequency doubler is activated in time at this frequency, the PLL will return to the normal operating mode shown in Figure 1. Conclusion From the above analysis, the following conclusions can be obtained:
The best way to eliminate parasitic mode oscillations during startup is to program the PLL to a frequency where a large Vtune value can be obtained. This will make the tuning voltage higher than the clamping voltage value. When this step is implemented, the Vtune diode clamping circuit will ensure that the tuning voltage is higher than the parasitic mode point where the resonant circuit is easy to enter. Turning off the frequency doubler will eliminate parasitic mode oscillations.
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