Electromagnetic compatibility design typically uses various control techniques. In general, the closer to the EMI source, the lower the cost of implementing EM control. The integrated circuit chip on the PCB is the most important source of energy for EMI, so EMI control in PCB and system-level design can be simplified if the internal features of the integrated circuit chip are well understood.
When considering EMI control, design engineers and PCB board design engineers should first consider the choice of IC chips. Certain features of integrated circuits such as package type, bias voltage, and chip: process technology (eg, CMoS, ECI) have a large impact on electromagnetic interference. The following will focus on the impact of ICs on EMI control.
Integrated circuit EMl source
The main sources of integrated circuit EMI in PCB are: EMl signal voltage and signal caused by the square wave signal frequency generated by the output terminal when the digital integrated circuit is switched from logic high to logic low or from logic low to logic high. Current electric field and magnetic field chip's own capacitance and inductance.
The square wave generated at the output of the integrated circuit chip contains a wide range of sinusoidal harmonic components, which constitute the EMI frequency component of interest to the engineer. The highest EMI frequency, also known as the EMI emission bandwidth, is a function of the signal rise time (rather than the signal frequency).
The formula for calculating the EMI emission bandwidth is: f=0.35/Tr
In the formula, the factory is the frequency, the unit is GHz; 7r is the signal rise time or fall time, the unit is ns.
It can be seen from the above formula that if the switching frequency of the circuit is 50 MHz and the rise time of the integrated circuit chip used is 1 ns, the highest EMI transmission frequency of the circuit will reach 350 MHz, which is much larger than the switching frequency of the circuit. And if the sink-rise time is 5 ribs Fs, then the circuit's highest EMI emission frequency will be as high as 700MHz.
Each voltage value in the circuit corresponds to a certain current, and each current has a corresponding voltage. When the output of the IC changes between logic high to logic low or logic low to logic high, these signal voltages and signal currents generate electric and magnetic fields, and the highest frequencies of these electric and magnetic fields are the emission bandwidth. The strength of the electric and magnetic fields and the percentage of external radiation are not only a function of the rise time of the signal, but also depend on the control of the capacitance and inductance of the signal path between the signal source and the load point. Therefore, the signal source is located on the PCB. Inside the sink, and the load is inside other ICs, these ICs may or may not be on the PCB. In order to effectively control EMI, it is necessary to pay attention not only to the sink; the capacitance and inductance of the tile itself, but also the capacitance and inductance existing on the PCB.
When the pot voltage between the signal voltage and the signal loop is not tight, the capacitance of the circuit is reduced, so that the suppression of the electric field is weakened, thereby increasing the EMI; the current in the circuit also has the same situation. The current is not the same as the return path; good, it is bound to increase the inductance on the loop, which enhances the magnetic field and eventually leads to an increase in EMI. This fully demonstrates that poor control of the electric field usually leads to poor magnetic field suppression. The measures used to control the electromagnetic field in the board are similar to those used to suppress the electromagnetic field in the IC package. As with PCB design, IC package design will greatly affect EMI.
A significant portion of the electromagnetic radiation in the circuit is caused by voltage transients in the power bus. When the output stage of the sink is: hopping and driving the connected PCB line to logic "high", the sink chip will draw current from the power supply to provide the energy required by the output stage. For the ultra-high frequency current generated by the continuous conversion of the IC, the de-rolling network on the power bus's PCB is stopped at the output stage of the sink. If the signal rise time of the output stage is 1.0 ns, then the IC must draw enough current from the power supply to drive the transmission line on the PCB within a short time P of 1.0 ns. The voltage transient on the power bus depends on the application on the power line j path. Sense, current absorbed, and current transfer time. The voltage transient is defined by the formula, L is the value of the inductance on the current transmission path; dj is the change of the current during the signal rise time interval; dz is the change of the transmission time of the d stream (the rise time of the signal).
Since the IC pin and the internal circuit are both part of the power bus, and the time taken to absorb the current and the output signal is also determined to some extent depending on the process technology of the sink, the selection of a suitable sink can largely control the Wei The three elements mentioned in the above formula.
The role of package features in electromagnetic interference control
IC packages typically include silicon-based chips, a small internal PCB, and pads. The silicon-based chip is mounted on a small 64 PCB, and the connection between the silicon-based chip and the pad is realized by the bonding wire. In some packages, the direct connection of the small PCB to the signal and the power supply and the package on the silicon-based chip can be realized. The connection between the corresponding pins, so that the external extension of the signal and power nodes on the silicon-based chip. Therefore, the power and signal transmission paths of the sink include a padding chip, a connection to a small PCB, a PCB trace, and input and output pins of the sink package. The control of capacitance and home feeling (corresponding to electric and magnetic fields) depends to a large extent on the design of the entire transmission path. Some design features will directly affect the capacitance and inductance of the entire IC chip package.
First look at the connection between the silicon-based chip and the internal small circuit board. Many sink chips use a bond wire to connect the solid neck silicon chip to the internal small circuit board, which is a very thin 6t wire between the silicon-based chip and the internal small circuit board. This technology is widely used because the silicon-based chip and the internal small circuit board have similar thermal expansion coefficients (CU). The chip itself is a silicon-based device with a thermal expansion coefficient and typical PCB material (such as epoxy resin). The coefficient of thermal expansion has a large difference. For example, if the electrical connection point of the silicon-based chip is directly mounted on the internal small PCB, then after a relatively short period of time, the internal temperature change of the IC package causes thermal expansion and contraction, and the connection in this way is broken. And failed. Bound wire is a kind of lead wire that adapts to this special environment. It can withstand the bending deformation of a large load and is not easy to break.
The problem with bonded wires is that an increase in the current loop area of ​​each signal or power line will result in an increase in the inductance value. A good design for obtaining a lower inductance value is to achieve a direct connection between the silicon-based chip and the internal PCB, that is, the connection point of the silicon-based chip is directly coupled to the pad of the PCB. This requires the use of a special PCB board based material that should have a very low coefficient of thermal expansion. The choice of this material will lead to an increase in the overall cost of the chip, so chips using this process technology are not common, but as long as the IC directly connecting the silicon-based chip to the carrier PCB exists: and is feasible in the design, So using such an IC device is a better choice.
In general, in sink package design, reducing the inductance and increasing the capacitance between the signal and the corresponding loop or between the power supply and ground is the primary consideration in the process of selecting an integrated circuit chip. For example, small-pitch surface mounts and high-pitch surface mounts: processes should be preferred to select sink chips that are packaged in a small-pitch surface mount process, and both types of surface mount process packages The IC chips are superior to the via lead type packages. The chip of the BGA package has the lowest lead inductance compared to any common package type. From the point of view of capacitance and inductance control, small packages and finer pitches often represent an increase in performance.
An important feature of lead structure design is the assignment of pins. Since the magnitude of the inductance and capacitance depends on the signal or the proximity between the power supply and the return path, consider enough return paths.
The power and ground pins should be allocated in pairs. Each power pin should have a corresponding ground pin adjacent to it, and multiple power pin and ground pin pairs should be assigned in this lead structure. Both of these features will greatly reduce the loop inductance between the power supply and ground, helping to reduce voltage transients on the power bus, thereby reducing EAdI. Due to customary reasons, many of the chips on the market do not completely follow the above design rules, but IC designers and manufacturers have a deep understanding of the advantages of this design method, so IC manufacturers are more likely to design and release new IC chips. Pay attention to the connection of the power supply.
Ideally, an adjacent signal return pin (such as a ground pin) needs to be assigned to each signal pin. This is not the case. Many IC vendors use other compromises. In the BGA package, a well-designed method is to set a signal return pin at the center of each set of eight signal pins. In this pin arrangement, between each signal and the signal return path. Only differ by one pin distance. For quad flat pack (QFP) or other gull-wing type ICs, it is unrealistic to place a signal return path at the center of the signal group, even if this is guaranteed every 4 to A signal is returned to the pin on the 6 pins. It should be noted that different sink technology may use different signal return voltages. Some ICs use ground pins (such as TIL devices) as the return path for signals, while some ICs use power pins (such as most ECI' devices) as signal return paths, and some ICs use power transistors at the same time. Foot and ground pins (such as most CMoS devices) act as a return path for the signal. Therefore, the design engineer must be familiar with the IC chip logic series used in the design to understand their related work.
The reasonable distribution of power and ground pins in the IC chip not only reduces EMI, but also greatly improves the groundboltnce effect. When the device driving the transmission line attempts to pull the transmission line to a logic low, the ground bounce reflects the transmission line above the logic low-closed level, and the bounce reflection may cause the circuit to fail or malfunction.
Another important issue in IC packaging is the PCB design inside the chip. The internal PCB is usually the largest component of the IC package. If the internal PCB design can achieve strict control of capacitance and inductance, it will greatly improve the system. Overall EMI performance. If this is a two-layer PCB board, at least one side of the PCB board is required to be a continuous ground plane layer, and the other side of the PCB board is a wiring layer of power and signal. More ideally, a four-layer PCB board has two layers in the middle, a power supply and a ground plane, and two outer layers as signal wiring layers. Since the PCB inside the sink package is usually very thin, the design of the four-layer board structure will lead to two high-capacitance, low-inductance wiring layers, which are particularly suitable for power distribution and input and output signals that need to be strictly controlled to enter and exit the package. A low-impedance planar layer can greatly reduce voltage transients on the power bus, which greatly improves EMI performance. This controlled signal line not only helps to reduce EMI, but also plays an important role in ensuring the integrity of the incoming and outgoing signals.
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